Free VHDL implementation of a PCI Brigde Core using
Xilinx Spartan-IIE FPGA

The free PCI core has been designed in the course of the developement of a modular and universally applicable FPGA-based PCI card project.

Design Structure:

The FPGA-Design consists of 3 main components:

• PCI master and slave control (configuration space etc.)
• Control unit of the so called "local bus", a freely definable non-multiplexed bus
• internal FIFO buffer for rate synchronisation, since the local bus can operate on an PCI-independent clock (e.g. faster than 33 MHz)
  

Figure 1: Main FPGA components

Characteristics of the PCI bus interface unit within the FPGA

• supports PCI-Master and PCI-Slave operation
• 33 MHz / 32Bit – PCI bus support
  
• complies with PCI-Spezification 2.1 (not officially tested/approved/certified !)
  
• Independent clock for PCI <- -> Local Bus by means of transmit and receive FIFO buffer
• configurable FIFO buffer size
  

Additional Features:

• I²C-Bus-Interface
• programmable clock controller for local bus clock
• variable / freely defniable local bus structure and protocol (adaption to various Microcontrollers and full custom chips possible)
  

In theorie, the following results could be achieved on a standard 32-bit / 33MHz PCI Bus:

Our test results however, show a maximum data rate in master mode (burst write) of 97,3 MByte/s using a standard 32-bit / 33MHz PCI Bus PC board.

Available Software (not for direct download):

• Device driver for Windows 2000 / Windows XP
• Test application
• Sourcecode of device driver and test application

Supported FPGAs:

• XILINX XC2S150E
• XILINX XC2S200E
• XILINX XC2S300E
• XILINX XC2S400E
• XILINX XC2S600E

Testing Platform (univeral and modular PCI board):

Figure 2  Design and Testing platform

Please use the following form to contact us, if you want to know more about our implementation or plan to reuse our free of charge VHDL PCI bridge.

© 2009     Thomas Martin Knoll     knoll@infotech.tu-chemnitz.de